sci.logic-noise-margin-CMOS Calculator
Calculates CMOS logic noise margin NM_H = V_OH − V_IH and NM_L = V_IL − V_OL from datasheet input/output voltage levels. Standard CMOS at 5 V: NM_H = NM_L ≈ 1.5 V — larger noise margins improve circuit immunity to interference; reduced Vdd in nanometre CMOS shrinks margins.
Inputs
- Voh V
- Electric potential difference (V). Drives current through a circuit. Household: 120 V (US) or 230 V (EU/UK).
- Vol V
- Electric potential difference (V). Drives current through a circuit. Household: 120 V (US) or 230 V (EU/UK).
- Vih V
- Reference formula or conversion factor shown for context.
- Vil V
- Reference formula or conversion factor shown for context.
- Vdd V
- Electric potential difference (V). Drives current through a circuit. Household: 120 V (US) or 230 V (EU/UK).
Results
- noise margin high NMH (V)
- Random or irrelevant variation in the measurement.
- noise margin low NML (V)
- Random or irrelevant variation in the measurement.
- worst-case noise margin (V)
- Random or irrelevant variation in the measurement.
- logic voltage swing (V)
- Electric potential difference between the two terminals (V). In AC systems, quoted as RMS — 230 V mains has a peak of ~325 V.
- NMH = VOH − VIH | NML = VIL − VOL
- Sample size or count used in the calculation.
- logic family comparison
- Sample size or count used in the calculation.
margin cmos high output noise